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SNIS143E – AUGUST 2006 – REVISED MARCH 2013
Logic Electrical Characteristics Digital DC Characteristics
Unless otherwise noted, these specifications apply for V DD =+3.0 to 3.6 Vdc. Boldface limits apply for T A = T J = T MIN to
T MAX ; all other limits T A = T J =+25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical (1)
Limits (2)
Units
(Limit)
SMBDAT, SMBCLK INPUTS
V IN(1)
V IN(0)
V IN(HYST)
Logical “1” Input Voltage
Logical “0”Input Voltage
SMBDAT and SMBCLK Digital Input
400
2.1
0.8
V (min)
V (max)
mV
Hysteresis
I IN(1)
I IN(0)
C IN
Logical “1” Input Current
Logical “0” Input Current
Input Capacitance
V IN = V DD
V IN = 0 V
0.005
? 0.005
5
±10
±10
μA (max)
μA (max)
pF
SMBDAT OUTPUT
I OH
V OL
High Level Output Current
SMBus Low Level Output Voltage
V OH = V DD
I OL = 4mA
10
0.4
μA (max)
V (max)
I OL = 6mA
0.6
(1)
(2)
Typical figures are at T A = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Logic Electrical Characteristics SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V DD =+3.0 Vdc to +3.6 Vdc, C L (load capacitance) on output lines = 80
pF. Boldface limits apply for T A = T J = T MIN to T MAX ; all other limits T A = T J = +25°C, unless otherwise noted.
The switching characteristics of the LM95241 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95241. They
adhere to but are not necessarily the SMBus bus specifications.
Symbol
Parameter
Conditions
Typical (1)
Limits (2)
Units
(Limit)
f SMB
SMBus Clock Frequency
100
10
kHz (max)
kHz (min)
t LOW
SMBus Clock Low Time
from V IN(0) max to V IN(0) max
4.7
μs (min)
25
ms (max)
t HIGH
t R,SMB
t F,SMB
t OF
t TIMEOUT
t SU;DAT
t HD;DAT
SMBus Clock High Time
SMBus Rise Time
SMBus Fall Time
Output Fall Time
SMBDAT and SMBCLK Time Low for Reset of
Serial Interface (5)
Data In Setup Time to SMBCLK High
Data Out Stable after SMBCLK Low
from V IN(1) min to V IN(1) min
See (3)
See (4)
C L = 400pF,
I O = 3mA (4)
1
0.3
4.0
250
25
35
250
300
μs (min)
μs (max)
μs (max)
ns (max)
ms (min)
ms (max)
ns (min)
ns (min)
1075
ns (max)
t HD;STA
Start Condition SMBDAT Low to SMBCLK Low
100
ns (min)
(Start condition hold before the first clock falling
edge)
t SU;STO
Stop Condition SMBCLK High to SMBDAT Low
100
ns (min)
(Stop Condition Setup)
t SU;STA
SMBus Repeated Start-Condition Setup Time,
0.6
μs (min)
SMBCLK High to SMBDAT Low
(1)
(2)
(3)
(4)
(5)
Typical figures are at T A = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
The output rise time is measured from (V IN(0) max + 0.15V) to (V IN(1) min ? 0.15V).
The output fall time is measured from (V IN(1) min - 0.15V) to (V IN(1) min + 0.15V).
Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t TIMEOUT will reset the LM95241's SMBus state machine,
therefore setting SMBDAT and SMBCLK pins to a high impedance state.
6
Product Folder Links: LM95241
Copyright ? 2006–2013, Texas Instruments Incorporated
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